FIG. 1 shows a multichannel-multiprotocol processor (MMP) of the prior art. In data networks, it is necessary in many applications to process sequences of data packets with different data packet protocols and with different data frame formats. As such, the data packets are received or transmitted by the multichannel processor via different data transmission channels. For this purpose, the multichannel-multiprotocol processor has input ports for the parallel reception of received data packets and output ports for transmitting transmit data packets. The multichannel processor performs data processing of the received data packets. This data processing typically comprises the fragmentation of large data packets to form transmit data packets of smaller data volume or, respectively, the assembly of a multiplicity of smaller data packets with a smaller data volume to form data packets having a large data format.
FIG. 2 shows a typical application for a multichannel-multiprotocol processor of the prior art. In the field of application shown in FIG. 2, a multichannel processor of the prior art is located in a UMTS transmission node B and in a radio network controller RNC which are connected to one another hardwired via data transmission lines. The UMTS transmission node receives data via a wireless transmission link from a mobile telephone and conducts data packets consisting of header and payload via data transmission lines to the corresponding multichannel-multiprotocol processor MMP within the radio network controller RNC. The transmission time necessary for transmitting data between the two multichannel-multiprotocol processors is a result of the ratio of the packet length and the predetermined data transmission rate.
Transmission time (ÜZ)=data packet length (bits): data transmission rate (megabits per second).
To reduce the transmission time ÜZ at the predetermined data transmission rate, the relatively large data packets are fragmented or taken apart in the multichannel-multiprotocol processor of the UMTS data transmission node B. In the example shown in FIG. 2, the large data packets are split into four data packet fragments and transmitted in parallel through four data transmission lines to the multichannel-multiprotocol processor within the radio network controller RNC. This results in a reduction of the data transmission time by a factor of 4. A typical data transmission rate in the example of the prior art shown in FIG. 2 is 2 megabits per second.
FIG. 3 shows a first computing architecture of a multichannel-multiprotocol processor of the prior art. A microprocessor is connected via buffers to input ports for receiving data packets and to output ports for transmitting transmit data packets. Data packets of different size are received, for example, by the multichannel-multiprotocol processor via corresponding input ports and temporarily stored as raw data in the buffer. The microprocessor accepts the received data packets via an internal processor bus and processes them in accordance with a program stored in a program memory, for the data processing of the received data packet. The processed data packet is then delivered to the corresponding output port via the processor bus and the buffer. The computing architecture shown in FIG. 3 makes it possible to process data packets with any data packet protocols and with any data packet formats, i.e. the computing architecture shown in FIG. 3 provides very great flexibility in the data processing. However, the MMP computing architecture shown in FIG. 3 has some serious disadvantages. The processor used is a full microprocessor with an extensive set of instructions. The circuit complexity is, therefore, very high for the MMP processor as shown in FIG. 3. The MMP processor according to FIG. 3 requires a large chip area due to the high circuit complexity of the processor. In addition, the power consumption of the MMP processor shown in FIG. 3 is very high. The data processing in the MMP processor shown in FIG. 3 is carried out in accordance with the software programs stored in the program memory. The software implementation of the multichannel-multiprotocol data processing of data packets is not suitable, in particular, for line card applications with very high data transmission rates. The MMP computing architecture shown in FIG. 3 is too slow for many applications.
FIG. 4 shows an alternative multichannel-multiprotocol processor computer architecture of the prior art. In the circuit arrangement shown in FIG. 4, received data packets are read in in parallel via the input ports and stored in a buffer. The data packets in each case comprise header and payload. In an identification circuit, the header data of the different data packets are compared with predetermined headers which are stored, for example, in a memory, and if the header type is known or stored, the received buffered data packet is correspondingly processed. The data processing consists, for example, of a fragmentation of a large data packet into a multiplicity of smaller data packets as shown in FIG. 4. As an alternative, the data processing can also consist of an assembly of many small data packets to form a large data packet. The data packet is split into header H and payload PL in accordance with the detected header type and supplied to the hardwired fragmentation circuit and header data processing circuit allocated to the header type detected. The processed header data H′ and the processed payload PL′ are then assembled again and buffered in an output data buffer as transmit data packets DP′. The assembled transmit data packets are then output via an assigned output port. The computer architecture for a multichannel-multiprotocol processor as shown in FIG. 4 has the serious disadvantage that data processing of data packets having an unknown header type is not possible. The data processing circuits, e.g. the fragmentation circuits for processing the payload, are hardwired. If the header type cannot be detected by the detection circuit, there is no further data processing. The computing architecture shown in FIG. 4 has relatively little circuit complexity and low power consumption. However, there is no flexibility whatsoever with respect to the multiprotocol data packets to be processed.
It is, therefore, the object of the present invention to create a multichannel-multiprotocol processor for processing data of multiprotocol data packets which, on the one hand, is capable of flexibly processing data packets with novel protocols and, on the other hand, has very little circuit complexity.